`timescale 1ns/1ns	
 

module Sync_FIFO_tb();
 
parameter   DATA_WIDTH = 8  ;			//FIFO位宽
parameter   DATA_DEPTH = 8 ;			//FIFO深度
parameter fifo_depth = 8;
parameter fifo_depth_bit = 3;
parameter data_width = 8;
 
reg									clk		;
reg									rst_n	;
reg                                 rst;
reg		[DATA_WIDTH-1:0]			data_in	;
reg									rd_en	;
reg									wr_en	;
						
wire	[DATA_WIDTH-1:0]			data_out;	
wire								empty	;	
wire								full	;
wire	[$clog2(DATA_DEPTH) : 0]	fifo_cnt;
 
 



Sync_FIFO Sync_FIFO_inst(
	.clk		(clk		),
	.reset		(~rst_n		),
	.dataIn	(data_in	),
	.rd_en		(rd_en		),
	.wr_en		(wr_en		),
                 
	.dataOut	(data_out	),	
	.empty		(empty		),	
	.full		(full		)		
);
 

initial begin
	clk = 1'b0;							
	rst_n <= 1'b0;						
	data_in <= 'd0;		
	wr_en <= 1'b0;		
	rd_en <= 1'b0;
//写8次数据	
	repeat(8) begin		
		@(negedge clk)begin		
			rst_n <= 1'b1;				
			wr_en <= 1'b1;		
			data_in <= $random;			
		end
	end
//读8次数据
	repeat(8) begin
		@(negedge clk)begin		
			wr_en <= 1'b0;
			rd_en <= 1'd1;
		end
	end
//写四次数据
	repeat(4) begin
		@(negedge clk)begin		
			wr_en <= 1'b1;
			data_in <= $random;	
			rd_en <= 1'b0;
		end
	end
//读四次数据
	forever begin
		@(negedge clk)begin		
			wr_en <= 1'b1;
			data_in <= $random;	
			rd_en <= 1'b1;
		end
	end
end
always #10 clk = ~clk;			//50m


endmodule
